| 1 | Convert between decimal and binary number systems. |
| 2 | Represent an arbitrary number in 2’s compliment binary. |
| 3 | Perform binary addition and/or subtraction, identifying any overflow. |
| 4 | Produce a Boolean logic expression from a gate-level logic diagram or vice versa. |
| 5 | Perform the negation of a Boolean logic expression. |
| 6 | Use a truth table to write a canonical SOP or canonical POS expression. |
| 7 | Draw a Karnaugh map and use it to create a simplified Boolean logic expression. |
| 8 | Draw a CMOS transistor-level diagram based on a Boolean logic expression. |
| 9 | Demonstrate knowledge of encoder and decoder operation. |
| 10 | Be able to synthesize a Boolean logic expression using combinational logic components such as decoders and multiplexers. |
| 11 | Implement gate delay in a timing diagram. |
| 12 | Demonstrate knowledge of multiplexer and demultiplexer operation. |
| 13 | Demonstrate knowledge of latch and flip flop operation. |
| 14 | Produce a timing diagram for arbitrary sequential logic. |
| 15 | Design a counter with an arbitrary counting sequence. |
| 16 | Find the static hazards in a given circuit and produce a hazard-free version of the circuit. |
| 17 | Produce a state machine for an arbitrary sequential logic circuit. |
| 18 | Demonstrate knowledge of multiplexer and demultiplexer operation. |
| 19 | Produce a state machine from a state transition table or vice versa. Be able to identify whether it is a Mealy or Moore machine. |
| 20 | Produce arbitrary flip-flop functionality using another arbitrary flip-flop and combinational logic. |
| 21 | Successfully implement behavioral HDL code on an FPGA. |
| 22 | Successfully implement a hierarchical HDL design on an FPGA. |
| 23 | Produce an animation on a FPGA’s 7-segment display by implementing an HDL design. |
| 24 | Produce an arbitrary Boolan logic function using physical 74-series chips. |
| 25 | Design a working state machine that implements functionality described in plain English. |
